1. Field of the Invention
This invention relates to a digital/analog conversion circuit.
2. Description of Related Art
FIG. 11 is a block diagram of an Ultra Wide Band (UWB) receiver or similar. First, signals received by the antenna 1 are selected in the frequency band of the band-pass filter BPF 2, and are amplified by the low-noise amplifier LNA 3. The amplified signals are demodulated by the quadrature demodulation portion 4, and are sent as baseband signals to the low-pass filter LPF 5. After high-frequency components are removed by the low-pass filter LPF 5, signals are amplified to a prescribed signal level by a variable-gain amplifier VGA 6. This variable-gain amplifier VGA 6 adjusts the gain according to the signal reception strength of the antenna 1.
Because the variable gain amplifier VGA used in such a receiver or similar generally has high gain, large offsets occur due to variability among elements. In a UWB receiver in particular, when an offset occurring in the VGA remains, reception characteristics are impacted through degradation of communication distances and in other ways, so that the offset voltage must be removed. One method to remove the offset voltage utilizes a digital/analog conversion circuit (hereafter called a “DAC”). A DAC is a circuit which converts a digital quantity into an analog quantity. A DAC must accurately output the analog quantity which corresponds to an input digital quantity. Moreover, the DAC output mode may be a current output mode or a voltage output mode.
Below, a current-output DAC 10 of the related art is explained using FIG. 12. The DAC 10 includes a digital/analog conversion portion 20 and a current mirror circuit 30.
The digital/analog conversion portion 20 includes a reference current source 21, a plurality of switches S22 to S29, and NMOS transistors MN21 to MN29. The switches S22 to S29 are turned on and off according to digital codes input to the DAC 10. The reference current supply 21 is connected between the power supply voltage terminal VDD (supplied voltage VDD) and the transistor MN21, and supplies a constant current I4 to the transistor MN21. The drains of the transistors MN22 to MN29 are connected to the switches S22 to S29, the sources are connected to the ground terminal GND, and the gates are connected to the reference current supply 21. Hence the transistors MN22 to MN29 form a current mirror circuit which employs the transistor MN21 as the input transistor. Hence the transistors MN22 to MN29 pass constant source currents according to the constant current I4.
The numerals “×1”, “×2”, “×4”, . . . appearing above the switches S22 to S29 indicate the factor by which the current flowing through the transistor MN22 is multiplied. Hence the current in transistor MN23 is 2 times the current flowing in transistor MN22, and the current in transistor MN24 is 4 times the current flowing in transistor MN22. This is achieved by adjusting the gate widths W of the transistors. Also, the ratios of the current amounts are digit weightings for each bit of an input digital code.
The current mirror circuit 30 includes PMOS transistors MP31 and MP32. The transistors MP31 and MP32 form a current mirror which uses the transistor MP31 as the input transistor. Hence a current mirror current I2 is output from the transistor MP32 according to the current I1 flowing in the transistor MP31.
Digital code signals are input to the DAC 10, and the switches S22 to S29 of the digital/analog conversion portion 20 are turned on and off according to the digital code. At this time, current flows in those transistors MN22 to MN29 which are connected to on-state switches. Currents flow in the transistors connected to the on-state switches in quantities according to the digit weightings of the bits of the digital code, as explained above. Hence the sum of the currents flowing in transistors connected to those switches which have been turned on according to the digital code is output from the digital/analog conversion portion 20 The summed current is the above-described current I1, and a mirror current I2 corresponding to the current I1 is output from the output terminal 40 as the output analog signal of the DAC 10.
Here, the potential at node P in FIG. 12 is expressed by the following equation.
      [          E      ⁢                          ⁢      1        ]                                            V            ⁡                          (              P              )                                =                                    V              DD                        -                                                                                21                                          MP                      ⁢                                                                                          ⁢                      31                                                        ⁢                                      L                                          MP                      ⁢                                                                                          ⁢                      31                                                                                                            K                    P                                    ⁢                                      W                                          MP                      ⁢                                                                                          ⁢                      31                                                                                            -                          V              TP                                                            (          1          )                    
Here, V(P) in equation (1) is the potential at node P, VDD is the power supply voltage, VTP is the PMOS transistor threshold voltage, IMP31 is the source-drain current of the transistor MP31, KP is the product of the carrier mobility (μP) and the gate oxide film capacitance (Cox) of PMOS transistors, LMP31 is the gate length of the transistor MP31, and WMP31 is the gate width of the transistor MP31.
In equation (1), the variable is IMP31. This is because the current IMP31 is the same as the current I1, so that the current IMP31 changes according to the input digital code.
Further, a transistor current in general can be represented as follows.
      [          E      ⁢                          ⁢      2        ]                                            I            DS                    =                                    1              2                        ⁢            K            ⁢                          W              L                        ⁢                                          (                                                      V                    GS                                    -                                      V                    T                                                  )                            2                                                            (          2          )                    
Here IDS in equation (2) is the drain-source current, K is the product of the carrier mobility and the gate oxide film capacitance for the PMOS or NMOS transistor, W is the transistor gate width, L is the transistor gate length, VGS is the gate-source voltage, and VT is the transistor threshold voltage. However, more rigorously, equation (2) should also include the factor (1+λVDS), as in equation (3) below.
      [          E      ⁢                          ⁢      3        ]                                            I            DS                    =                                    1              2                        ⁢            K            ⁢                          W              L                        ⁢                                          (                                                      V                    GS                                    -                                      V                    T                                                  )                            2                        ⁢                          (                              1                +                                  λ                  ⁢                                                                          ⁢                                      V                    DS                                                              )                                                            (          3          )                    
Because of this factor (1+λVDS), when there is fluctuation in VDS, the current IDS also fluctuates. This fluctuation is called the Early effect.
As is seen from equation (1), the potential V(P) at node P fluctuates due to IMP31(=I1). In the transistors MN22 to MN29, this fluctuation in the potential V(P) becomes fluctuations in VDS in equation (3), so that IDS fluctuates. Hence the balance of the digit weightings for each bit of an input digital code is worsened, and there is the problem that the linearity of the digital/analog conversion deteriorates. Indices indicating deterioration of this linearity include Integral Non Linearity (INL) and Differential Non Linearity (DNL).
In Japanese Unexamined Patent Application Publication No. 2002-9623, technology is disclosed which has as an object improvement of the precision of the current mirror ratio of a current mirror circuit. However, in Japanese Unexamined Patent Application Publication No. 2002-9623, the circuit configuration is such that there is voltage fluctuation at the node between the digital/analog conversion portion (D/A conversion portion) and the current mirror (CM), and due to the abovementioned Early effect, there is the problem that the linearity of digital/analog conversion deteriorates.